10BASE-T1S Physical Coding Sublayer (PCS) Operation and High-Level Encoding Methods

Compared to most other modern forms of Ethernet, the PCS of 10BASE-T1S is significantly reduced in complexity due to a 10 Mbit/s operation, using a simple 2-level binary signal and Differential Manchester Encoding (DME) at the physical layer. These things eliminate the need for much of the complexity in the PCS, including any Decision Feedback Equalizer (DFE), Forward Error Correction (FEC), Echo Cancellation, and other complexities. This is true even if the PHY is run in the optional point-to-point full-duplex mode. DME is discussed in more detail in the next section, but the simplifications in the PCS in comparison to 100BASE-T1 are included in the following table:

Differential Manchester Encoding, 2-level signaling and 10 Mbit/s operation
simplify a 10BASE-T1S PHY in comparison to other Ethernet networks.

MII, PCS and PMA data flow diagram.

Use of Collision Detect COL and Carrier Sense CRS at the MII

Collision detection and carrier sense were needed before full-duplex operation became the norm and Switch is used for nearly all Ethernet forms. Two signals in the standard MII interface still exist in support of this. They are COL and CRS. In 10BASE-T1S half-duplex mode, a transmitter must wait for its Transmit Opportunity (TO) before attempting to transmit. This leads to a possible delay when a host may attempt to transmit and when the PHY has a TO available as well. To eliminate the need for large buffering in the PHY, CRS and the COL signals are used in the following way. The CRS is true when there is energy on the line. In other words, there is activity and MAC must wait. If the MAC forwards data to the PHY, there is still a chance that a different node starts transmitting while waiting for a TO. If this occurs, COL is asserted to force the MAC connected to the MII to go into the random backoff mode. The maximum backoff time in the MAC is shorter than the minimum Ethernet frame duration, ensuring this logic does not cause a missed TO for data entering the PHY.

Scrambler

A 17-bit self-synchronizing scrambler is used to improve EMC characteristics. On incoming, the scrambler is performed prior to any Special Function symbols like the BEACON, COMMIT, and others. By doing this, some EMC performance is lost; however, this is necessary to preserve the 5B Special Function binary pattern necessary for other PCS and PMA blocks to recognize

Self Synchronizing Scrambler.

4B/5B Encoding

Four bits from the MII are converted to five bits to allow some special symbols to be transmitted. Some of these were mentioned in the section on the PLCA. We described 4B/5B Block Encoding in the previous section 7.3.3; therefore, refer to it for more information. The 4/5 ratio also supports an easy rate change with a 25MHz clock without additional logic. 4B/5B encoding has good automotive EMC/EMI characteristics and can support PoDL.

4B/5B Symbol Encoding.

Intrepid’s 10BASE-T1S Hardware